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CASTNESS'07 Workshop and School

Computing Architectures and Sw Tools for Numerical Embedded Scalable Systems

15th-17th January 2007 in Roma - Italy

Links to CASTNESS '07 flyer and program

Programme Committee

Ahmed Jerraya, Rainer Leupers, Pier Stanislao Paolucci, Lothar Thiele, Piero Vicini.

CASTNESS'07 OBJECTIVE

The objective is cross-dissemination among SHAPES, projects like SARC and AETHER, HARTES, the APE Massive Parallel Processor initiative, and the academic and industrial research community sharing the topics addressed by those project. The community addressed by ARTIST2 and ARTEMIS are warmly welcome.

During CASTNESS'07 it will be also presented the INFN Petaflops Ape project proposal, which is assumed to start during 2007, allowing the actual exploitation onto a physically working peta-flops system.

CASTNESS'07 started as a dissemination event promoted by SHAPES (Scalable Software Hardware Architecture Platform for Embedded Systems): a FET-ACA IST-FP6 Integrated Project started in January 2006. The objective of SHAPES is to design a Tiled HW Architecture supported by a Communication Centric System SW, benchmarked on Embedded Numerical Applications (visit http://www.shapes-p.org).

AGENDA 15 January 2007 -FIRST DAY, WORKSHOP - short talks (20' each + 5' discussion)

REGISTRATION

  • 07:45-08:30 (Aula M. Conversi - Dip. Fisica - Building Guglielmo Marconi)

OPENING WELCOME

  • 08:30-08:40 - INFN and Dip. Fisica Roma, Univ. “La Sapienza”

OPENING SPEECH

  • 08:40-09:00 - Luca Benini - Universita' di Bologna - Communication Centric Architectures

SARC Project

  • 09:05-09:25 - G.N.Gaydadjiev - TU Delft - SARC Overview

short break 09:30-09:40

AETHER Project

  • 09:40-10:00 - Christian Gamrat - CEA - The concept of Self-Adaptive computing in AETHER
  • 10:05-10:25 - Sven-Bodo Scholz - Univeristy of Hertfordshire(UK) - Software environnement for self-adaptive computing systems

coffe break 10:30-10:55

SHAPES Project (part I)

  • 10:55-11:15 - Pier S. Paolucci - ATMEL and INFN - SHAPES Tiled HW Architecture
  • 11:20-11:40 - Lothar Thiele - ETHZ - Scalable Software Construction in SHAPES
  • 11:45-12:05 - Ahmed Jerraya - TIMA - Programming Models and Hardware dependant Software Abstraction for MPSoC

short break 12:10-12:20

  • 12:20-12:40 - Rainer Leupers - RWTH-AACHEN - MPSoC Virtual Platforms
  • 12:45-13:05 - Gert Goossens - TARGET - Generation techniques of VLIW Compilers

Buffet Lunch 13:10-14:00

SHAPES Project (part II)

  • 14:00-14:20 - Dominique Ragot - THALES - A Software Infrastructure for Managing Complexity and Performance of Applications in MPSoC
  • 14:25-14:45 - Marcello Coppola - ST Microelectronics - STNOC: An evolution towards MPSoC era

short break 14:50-15:00

  • 15:00-15:20 - Davide Rossetti/Piero Vicini - INFN - From the Distributed Network Processor of SHAPES to a Petaflops Ape proposal

EUROPEAN COMMISSION: FP7

  • 15:25-15:45 - Patrick Van Hove - European Commission

HARTES Project

  • 15:50-16:10 - Piergiovanni Bazzana - Atmel Roma - HARTES (Holistic Approach to Real Time Embedded Systems) Overview

coffe break 16:15-16:40

  • 16:40-17:00 - Donatella Sciuto - Polimi - Modeling and Simulation of System-on-Chip Platforms
  • 17:05-17:25 - Wayne Luk - Imperial College - Reconfigurable Processor Design

MORPHEUS Project

  • 17:30-17:50 - Philippe Bonnot - Thales TRT - Application Programming design flow for the Morpheus heterogeneous dynamically reconfigurable platform

short break 17:55-18:05

INVITED SPEAKER

  • 18:05-18:25 - Mauro Olivieri - Univ Roma1 - Dealing with Dynamic and Leakage Energy Dissipation trough Code Optimization and Scratchpad Memories

CLOSURE SPEECH

  • 18:30-18:50 - Peter Marwedel - Get Rid of Caches: Compiler Techniques for Scratch-pads - Univ Dortmund+ICD

VISIT TO INFN APE

  • 18:55-19:30 VISiT? TO APE MASSIVE PARALLEL COMPUTING INSTALLATION

SOCIAL DINNER

  • 21:00-...

AGENDA 16-17 January 2007 -2nd and 3rd DAY, SCHOOL: lessons (2h each)

This year the focus of the school focuses on tools and methodologies for automated generation of System Software.

Link to SCHOOL ABSTRACTS

January 16th

  • Peter Marwedel - Univ Dortmund+ICD - Memory-architecture aware compilation (2h)
  • Lothar Thiele, Iuliana Bacivarov - ETHZ - Design Space Exploration for MPSoC (40'); Modular Performance Analysis - Models, Methods and Scenarios (40'); Modular Performance Analysis - Real-Time Calculus (40').
  • Gert Goossens - TARGET Compiler Technologies - Leuven - How a Retargetable Tool Suite for ASIP Design Enables Next-Generation Multi-Processor Systems-on-Chip (2h)

January 17th

  • Katalin Popovici, Xavier Guérin, Frédéric Rousseau & Wassim Youssef - TIMA GRENOBLE - Modeling MPSoC Running Multithread Software at Different Abstraction Levels Using Simulink & systemC (40'); Multithread Software Code Generation from Simulink (40'); Application of Software Code Generation Flow from Simulink to Diopsys Platform (40').
  • Torsten Kempf - RWTH-AACHEN - MPSoC Exploration Technology (2h)
  • Pier Stanislao Paolucci - ATMEL and INFN, Andrea Ricciardi and Elena Pastorelli - ATMEL Roma - Architecture of mAgicV VLIW DSP and Diopsis 940 MPSoC (40'); Generation of the optimizing mAgicV VLIW DSP C Compiler (40'); Generation of optimized DSP library written in C for mAgicV VLIW DSP (40');

Participants List

CASTNESS 07 Participants List This list is ordered according to the registration date

Workshop (first day) - Max 80 partecipants

Patrick van Hove, European Commission - Luca Benini, Universita' di Bologna - Pier S. Paolucci, ATMEL and INFN - Ahmed Jerraya, TIMA - Lothar Thiele, ETHZ - Dominique Ragot, THALES - Rainer Leupers, RWTH-AACHEN - Gert Goossens, TARGET - Davide Rossetti, INFN - Marcello Coppola, ST Microelectronics - Christian Gamrat, CEA - Sven Bodo-Scholz, University of Hertfordshire(UK) - G. N. Gaydadijev, TU Delft - Philippe Bonnot, THALES - Piergiovanni Bazzana, Atmel - Donatella Sciuto, Polimi - Wayne Luk, Imperial College (UK) - Peter Marwedel, ICD University of Dortmund - Mauro Olivieri, Uni Roma1 - Piero Vicini, INFN - Iuliana Bacivarov, ETHZ - Kai Huang, ETHZ - Katalin Popovici, TIMA, France - Xavier Guérin, TIMA, France - Frédéric Rousseau, TIMA, France - Wassim Youssef, TIMA, France - Torsten Kempf, RWTH Aachen - Andrea Ricciardi, ATMEL Roma - Elena pastorelli, ATMEL Roma - Ben Altieri, Atmel - Anne-Marie Fouilliart, THALES - Alessandro Lonardo, INFN - Mersia Perra, INFN - Carlo Sidore, INFN - Francesca Lo Cicero, INFN - Alberto Dell'Olio, ATMEL - Federico Aglietti, ATMEL - Lei Gao, RWTH Aachen - Stefan Kraemer, RWTH Aachen - Jeronimo Castrillon, RWTH Aachen - Jianjiang Ceng, RWTH Aachen - Luigi Raffo, DIEE Uni CA - Gianni Mereu, DIEE Uni CA - Francesca Palumbo, DIEE Uni CA - Francesco Menichelli, DIE Uni Roma1 - Simone Smorfa, DIE Uni Roma1 - Francesco Simula, INFN - Matthias Mueller(*), University of Tuebingen - Marcelo Santos(*), Malardalen University-Sweden - Jose Coutinho(*), Imperial College London - William Osborne(*), Imperial College London - Matti Juvonen(*), Imperial College London - Luca Arena, Università La Sapienza - Madhura Purnaprajna(*), University of Paderborn,Germany - Paolo Palazzari, ENEA & Ylichron Srl, Italy - Giorgio Brusco, Ylichron Srl, Italy - Andrea Biagioni, INFN - Sergio De Luca, INFN - Ottorino Frezza, INFN - Laura Tosoratto, INFN - Marco Cesati, Uni Roma2 - Emiliano Betti, Uni Roma2 - Daniel P. Bovet, Uni Roma2 - Nicola L'Insalata, Uni Pisa - Michele Casula, Uni Pisa - Francesco Vitullo, Uni Pisa - Esa Petri, Uni Pisa - Bruno Jofret, Scilab (INRIA), France - Valerio Galli, Ericsson Roma - Andrea Marongiu(*), Uni BO - Alessandro Dalla Torre(*), Uni BO - Martino Ruggero(*), Uni BO - Luca Fanucci, Uni Pisa - Maruccia Giuseppe, ST Microelectronics - Mario Gigliotti, Università La Sapienza - Luca Giancane, Università La Sapienza - Giuseppe Scotti, Università La Sapienza - Federico Goller, Università La Sapienza - Michael Beckinger, Fraunhofer Inst. - Roberto Ammendola, INFN Roma2

School (second and third day) FINAL

Speakers: Peter Marwedel, Lothar Thiele, Iuliana Bacivarov, Kai Huang, Gert Goossens, Katalin Popovici, Xavier Guérin, Frédéric Rousseau, Wassim Youssef, Torsten Kempf, Pier Stanislao Paolucci, Andrea Ricciardi, Elena Pastorelli

Federico Aglietti, ATMEL Roma - Lei Gao, RWTH Aachen - Jianjiang Ceng, RWTH Aachen - Jeronimo Castrillon, RWTH Aachen - Luigi Raffo, Uni CA - Gianni Mereu, Uni CA - Francesca Palumbo, Uni CA - Francesco Menichelli, Uni Roma1 - Simone Smorfa, Uni Roma1 - Francesco Simula, INFN - Mersia Perra, INFN - Alessandro Lonardo, INFN - Davide Rossetti, INFN - Francesca Lo Cicero, INFN - Carlo Sidore, INFN - Matthias Muller (*), Uni of Tuebingen - Andrea Michelotti, ATMEL ROMA - Marcelo Santos(*), Malardalen University-Sweden - Jose Coutinho(*), Imperial College London - William Osborne(*), Imperial College London - Matti Juvonen(*), Imperial College London - Luca Arena, Università La Sapienza - Roberto Sigismondi, Uni ROMA1 - Madhura Purnaprajna(*), University of Paderborn,Germany - Giorgio Brusco, Ylichron Srl, Italy - Stefan Kramer, RWTH Aachen - Marco Cesati, Uni Roma2 - Emiliano Betti, Uni Roma2 - Nicola L'Insalata, Uni PI - Michele Casula, Uni PI - Francesco Vitullo, Uni PI - Esa Petri, Uni PI - Ivano Salvemini, Uni Roma1 - Bruno Jofret, Scilab (INRIA) - Andrea Marongiu(*), Uni BO - Alessandro Dalla Torre(*), Uni BO - Martino Ruggero(*), Uni BO - Alberto Dell'Olio, ATMEL - Maruccia Giuseppe, ST Microelectronics - Michael Beckinger, Fraunhofer Inst. - Roberto Ammendola, INFN Roma2 - Dominique Ragot, THALES - Andrea Biagioni, INFN - Sergio De Luca, INFN - Ottorino Frezza, INFN - Laura Tosoratto, INFN

(*) (ARTIST2 Grant)

CASTNESS07_flyer, CASTNESS07_program, CASTNESS07_presentations

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