Personal tools
Views
From Euretile
Jump to: navigation, search

CASTNESS'08 Workshop and School

Computing Architectures and Sw Tools for Numerical Embedded Scalable Systems
15th-18th January 2008 - Roma - Italy.

PROGRAMME COMMITTEE

The programme committe is composed of SHAPES and HARTES members.

  • SHAPES: Ahmed Jerraya, Rainer Leupers, Pier Stanislao Paolucci, Frederic Rousseau, Lothar Thiele, Piero Vicini.
  • HARTES: Piergiovanni Bazzana, Volker Hahn, Wayne Luk, Francesco Piazza, Remond Sautreau, Donatella Sciuto.

LOCAL ORGANIZING COMMITTEE

Eugenio Faggioli, Gigliola Gori, Marisa Iannarelli, Roberto Marega, Pier Stanislao Paolucci, Mersia Perra, Piero Vicini.

CASTNESS'08 OBJECTIVE

  • to provide training about the future of multi-processor/adaptable embedded systems (system SW, HW architectures, applications)
  • cross-dissemination among european projects: SHAPES, HARTES, SARC, AETHER, MORPHEUS, the APE Massive Parallel Processor initiative, and the academic and industrial research community sharing the topics addressed by those project. The community addressed by ARTIST2, HIPEAC and ARTEMIS are warmly welcome.

CASTNESS'08 is a dissemination event jointly organized by the European Integrated Research Projects:

During the 4 days event, a meeting room is available for parallel meeting sessions. Please proceed to CastNess08ParallelMeetingSessions to make your meetings proposal.

CASTNESS'08 PRESENTATIONS

To download the presentation of the second edition proceed to CASTNESS08_presentations

AGENDA

Tuesday 15 January 2008: WORKSHOP
Event Speaker Name Affiliation Duration Start End
REGISTRATION 01.00 08.00 09.00
WELCOME 00.05 09.00 09.05
CASTNESS'08 AGENDA Pier Stanislao PAOLUCCI ATMEL Roma and INFN Roma, IT 00.10 09.05 09.15
HARTES: overview Piergiovanni BAZZANA ATMEL Roma, IT 00.20 09.15 09.35
HARTES: sw architecture overview Koen BERTELS TU Delft, NL 00.20 09.35 09.55
SHORT BREAK 00.15 09.55 10.10
HARTES: sw partitioning overview Fabrizio FERRANDI Politecnico di Milano, IT 00.20 10.10 10.30
HARTES: Exploring and optimising reconfigurable designs Wayne LUK Imperial College London, UK 00.20 10.30 10.50
HARTES: application overview Francesco PIAZZA Università Politecnica delle Marche, IT 00.20 10.50 11.10
COFFEE BREAK 00.30 11.10 11.40
HARTES: in-car audio algorithms Francesco PIAZZA Università Politecnica delle Marche, IT 00.20 11.40 12.00
HARTES: hw application platform Raffaele TRIPICCIONE Università di Ferrara, IT 00.20 12.00 12.20
LUNCH 01.20 12.20 13.40
SHAPES: multi-tiled HW architecture overview Pier Stanislao PAOLUCCI ATMEL Roma and INFN Roma, IT 00.20 13.40 14.00
SHAPES: sw architecture overview Lothar Thiele ETHZ-Zurich, CH 00.20 14.00 14.20
SHAPES: application overview Thomas SPORER FRAUNHOFER IDMT, D 00.20 14.20 14.40
SHORT BREAK 00.15 14.40 14.55
SHAPES: VSP - Virtual Shapes Platform Rainer LEUPERS RWTH AACHEN, D 00.20 14.55 15.15
SHAPES: DOL - Distributed Operation Layer Iuliana BACIVAROV ETHZ-Zurich, CH 00.20 15.15 15.35
SHAPES: Overview of the Software Stack Generation Starting from High Level Application Model Frederic ROUSSEAU TIMA, FR 00.20 15.35 15.55
COFFEE BREAK 00.30 15.55 15.25
SHAPES: CHESS C Compiler for shapes Gert GOOSSENS TARGET Compiler Technology, B 00.20 16.25 16.45
SHAPES: Real-Time support for Heterogeneous SoC Dominique RAGOT THALES, FR 00.20 16.45 17.05
SHAPES: Spidergon STNoC: the communication infrastructure for Multiprocessor architectures Marcello COPPOLA ST Microelectronics, FR 00.20 17.05 17.25
SHAPES: DNP - Distributed Network Processor Piero VICINI INFN, IT 00.20 17.25 17.45


Wednesday 16 January 2008: WORKSHOP
Event Speaker Name Affiliation Duration Start End
SARC: Some more general overview about SARC Georgi N. GAYDADJIEV TU Delft, NL 00.20 09.00 09.20
SARC: The SARC architecture Alex RAMIREZ Universitat Politècnica de Catalunya/BSC, ES 00.20 09.20 09.40
SARC: The SARC programming model Xavier MARTORELL Universitat Politècnica de Catalunya/BSC, ES 00.20 09.40 10.00
SHORT BREAK 00.15 10.00 10.15
AETHER: From Reconfigurable to Self-Adaptive computing Christian GAMRAT CEA LIST 00.20 10.15 10.35
AETHER: Self-Adaptive Implementation using dynamically reconfigurable hardware Katarina PAULSSON U. KARLSRUHE 00.20 10.35 10.55
AETHER: An operating environment for self-adaptive computing elements Jean-Philippe DIGUET U. BRETAGNE SUD 00.20 10.55 11.15
COFFEE BREAK 00.30 11.15 11.45
MORPHEUS: overview Philippe BONNOT THALES 00.20 11.45 12.05
Invited Talk: Programming Heterogeneous MPSoC? Architectures Ahmed JERRAYA CEA LETI 00.20 12.05 12.25
SHAPES: DEMO of programming/simulation environment on Multi-loudspeaker WFS 00.15 12.25 12.40
LUNCH 01.00 12.40 13.40
Invited Talk: Additive Musical Synthesis Lorenzo SENO & Piergiovanni BAZZANA CRM & ATMEL 00.20 13.40 14.00
Invited Talk: Acoustic scene analysis and distant-talking speech recognition for smart home Maurizio OMOLOGO FBK-IRST 00.40 14:00 14.40
SHORT BREAK 00.15 14.40 14.55
Invited Talk: Wave Field Synthesis - Theory, Applications and Market Thomas SPORER FRAUNHOFER IDMT, D 00.40 14.55 15.35
Research on massive ICT systems Jean-Marie AUGER European Commission 00.20 15.35 15.55
Computing Systems in FP7: Call-1 results and future outlook Panagiotis TSARCHOPOULOS European Commission 00.20 15.55 16.15
COFFEE BREAK 00.30 16.15 16.45
BRAINSTORMING SESSION: panel + feedback of all participants 00.45 16.45 17.30
Invited Talk Khaled DOUZANE SCALEO CHIP 00.20 17.30 17.50


Thursday 17 January 2008: SCHOOL
Event Speaker Name Affiliation Duration Start End
FCM3-SoC Emulation and Fast Prototyping Platform Khaled DOUZANE SCALEO Chip 00.45 09.00 09.45
SHORT BREAK 00.15 09.45 10.00
Efficient Design Space Exploration Lothar THIELE ETH-Zurich 00.45 10.00 10.45
COFFEE BREAK 00.30 10.45 11.15
Software Stack Generation for MPSoC Starting from High Level Application Model Xavier GUERIN & Alexandre CHUREAU TIMA 00.45 11.15 12.00
SHORT BREAK 00.15 12.00 12.15
Implementation Refinement from High Level Application Model Alexandre CHAGOYA-GARZON & Patrice GERIN TIMA 00.45 12.15 13.00
LUNCH 01.00 13.00 14.00
Tools for ASIP and MPSoC development Stefan KRAEMER RWTH-AACHEN 00.45 14.00 14.45
SHORT BREAK 00.15 14.45 15.00
Hybrid simulation framework for fast application simulation Lei GAO RWTH-AACHEN 00.45 15.00 15.45
SHORT BREAK 00.15 15.45 16.00
Wave Field Synthesis Michael BECKINGER FRAUNHOFER IDMT 00.45 16.00 16.45
COFFEE BREAK 00.30 16.45 17.15
Chess Retargetable Compiler Gert GOOSSENS TARGET Compiler Technology 00.45 17.15 18.00


Friday 18 January 2008: SCHOOL
Event Speaker Name Affiliation Duration Start End
Distributed Network Processor Davide ROSSETTI INFN 00.45 10.00 10.45
COFFEE BREAK 00.30 10.45 11.15
Zebu: a compiler framework for MPSoCs architectures - I Fabrizio FERRANDI POLIMI 00.45 11.15 12.00
SHORT BREAK 00.15 12.00 12.15
Zebu: a compiler framework for MPSoCs architectures - II Fabrizio FERRANDI POLIMI 00.45 12.15 13.00
LUNCH 01.00 13.00 14.00
Implementation Refinement from High Level Application Model Alexandre CHAGOYA-GARZON & Patrice GERIN TIMA 00.45 12.15 13.00
LUNCH 01.00 13.00 14.00
Optimizing task and data representations Tim TODMAN IMPERIAL 00.45 14.00 14.45
SHORT BREAK 00.15 14.45 15.00
Codesign for heterogeneous systems Yuet Ming LAM IMPERIAL 00.45 15.00 15.45
SHORT BREAK 00.15 15.45 16.00
Implementing DSP Algorithms in NU-Tech for Real Time Applications Ariano LATTANZI LEAFF 00.45 16.00 16.45
COFFEE BREAK 00.30 16.45 17.15
Dissection of a high-perf. audio application on a RISC + floating-point VLIW DSP MPSOC: Diopsis 940 Stefano FASCIANI ATMEL 00.45 17.15 18.00


Participant List

Workshop (max 120pp- 1st and 2nd day - 2008, January 15-16)
Name Affiliation State
Jean-Marie Auger European Commision
Panagiotis Tsarchopoulos European Commision
Pier Stanislao Paolucci ATMEL Roma and INFN Italy
Piergiovanni Bazzana ATMEL Roma Italy
Koen Bertels TU Delft The Netherlands
Fabrizio Ferrandi Politecnico di Milano Italy
WaYne Luk Imperial College London United Kingdom
Volker Hahn Fraunhofer IGT Germany
Francesco Piazza Università politecnica delle Marche Italy
Lothar Thiele ETH-Zurich Switzerland
Thomas Sporer Fraunhofer IDMT Germany
Rainer Leupers EWTH-AACHEN Germany
Iuliana Bacivarov ETH-Zurich Switzerland
Frédéric Rousseau TIMA France
Gert Goossens TIMA France
Dominique Ragot THALES France
Marcello Coppola ST Microelectronics France
Piero Vicini INFN Italy
G.N. Gaydadjiev Technische Universiteit Delft The Netherlands
Alex Ramirez Universitat Politècnica de Catalunya/BSC Spain
Xavier Matrorel Universitat Politècnica de Catalunya/BSC Spain
Christian Gamrat CEA France
Katarina Paulsson Univeritat Karlsruhe Germany
Jean -Philippe Diguet Universitè de Bretagne-Sud France
Philippe Bonnot THALES France
Ahmed Jerraya CEA/LETI/DCIS/ MINATEC France
Khaled Douzane SCALEO CHIP France
Maurizio Omologo FBK-IRST Italy
Lorenzo Seno Centro Ricerche Musicali Italy
Xavier Guérin TIMA France
Alexandre Chureau TIMA France
Alexandre Chagoya-Garzon TIMA France
Patrice Gerin TIMA France
Stefan Kraemer RWTH-AACHEN Germany
Lei Gao RWTH-AACHEN Germany
Michael Beckinger Fraunhofer IDMT Germany
Davide Rossetti INFN Roma Italy
Tim Todman Imperial College London United Kingdom
Yuet Ming Lam Imperial College London United Kingdom
Stefano Fasciani ATMEL Roma Italy
Muhamad Rashid Thomson Silicon Components France
Roberto Marega HARTES Italy
Francesca Palumbo Università degli Studi di Cagliari Italy
Christoph Schumacher RWTH-AACHEN Germany
Weihua Sheng RWTH-AACHEN Germany
Alberto Dell'Olio ATMEL Roma Italy
Alessio Turetta Università di Genova Italy
Emiliano Betti Università di Roma Tor Vergata Italy
Giuseppe Maruccia ST Microelectronics France
Alessandro Lonardo INFN Roma Italy
Mersia Perra INFN Roma Italy
Carlo Sidore INFN Roma Italy
Francesca Lo Cicero INFN Roma Italy
Sergio De Luca INFN Roma Italy
Ottorino Frezza Eurotech Italy
Laura Tosoratto INFN Roma Italy
Roberto Amendola INFN Roma Italy
Andrea Michelotti ATMEL Roma Italy
Gianni Mereu Università degli Studi di Cagliari Italy
Wolfgang Haid ETH-Zurich Switzerland
Kai Huang ETH-Zurich Switzerland
Anne-Marie Fouilliart THALES Communications France
Simon Thabuteau THALES Communications France
Mangesh Chitnis Scuola Superiore Sant'Anna Italy
Francesco Vitullo Università di Pisa Italy
Simone Secchi Università di Cagliari Italy
Paolo Meloni Università di Cagliari Italy
Luca Giancane "Sapienza” Università di Roma Italy
Giuseppe Scotti "Sapienza” Università di Roma Italy
Mario Gigliotti "Sapienza” Università di Roma Italy
Roberto Romanato "Sapienza” Università di Roma Italy
Ben Altieri ATMEL Roma Italy
Daniele Teti "Sapienza” Università di Roma Italy
Gianmarco Fiabane "Sapienza” Università di Roma Italy
Andrea Biagioni INFN Roma Italy
Federico Massaioli CASPUR Italy
Francesco Simula INFN Roma Italy
Giovanni Iacovoni “Sapienza” Università di Roma Italy
Pier Francesco Foglia Università di Pisa Italy
Mauro Olivieri “Sapienza” Università di Roma Italy
Cinti Alessandro “Sapienza” Università di Roma Italy


School (max 80pp-3rd and 4th day - 2008, January 17-18)
Name Affiliation State
Pier Stanislao Paolucci ATMEL Roma and INFN Italy
Piergiovanni Bazzana ATMEL Roma Italy
Lothar Thiele ETH-Zurich Switzerland
Thomas Sporer Fraunhofer IDMT Germany
Iuliana Bacivarov ETH-Zurich Switzerland
Frédéric Rousseau TIMA France
Piero Vicini INFN Roma Italy
Khaled Douzane SCALEO CHIP France
Xavier Guérin TIMA France
Alexandre Chureau TIMA France
Alexandre Chagoya-Garzon TIMA France
Patrice Gerin TIMA France
Stefan Kraemer RWTH-AACHEN Germany
Lei Gao RWTH-AACHEN Germany
Michael Beckinger Fraunhofer IDMT Germany
Davide Rossetti INFN Roma Italy
Tim Todman Imperial College London United Kingdom
Yuet Ming Lam Imperial College London United Kingdom
Fabrizio Ferrandi Politecnico di Milano Italy
Ariano Lattanzi LEAFF-Università Politecnica delle Marche Italy
Stefano Fasciani ATMEL Roma Italy
Muhamad Rashid Thomson Silicon Components France
Roberto Marega HARTES Italy
Francesca Palumbo Università degli Studi di Cagliari Italy
Christoph Schumacher RWTH-AACHEN Germany
Weihua Sheng RWTH-AACHEN Germany
Alberto Dell'Olio ATMEL Roma Italy
Alessio Turetta Università di Genova Italy
Emiliano Betti Università di Roma Tor Vergata Italy
Giuseppe Maruccia ST Microelectronics France
Alessandro Lonardo INFN Roma Italy
Mersia Perra INFN Roma Italy
Carlo Sidore INFN Roma Italy
Francesca Lo Cicero INFN Roma Italy
Sergio De Luca INFN Roma Italy
Ottorino Frezza Eurotech Italy
Laura Tosoratto INFN Roma Italy
Roberto Amendola INFN Roma Italy
Andrea Michelotti ATMEL Roma Italy
Gianni Mereu Università degli Studi di Cagliari Italy
Wolfgang Haid ETH-Zurich Switzerland
Kai Huang ETH-Zurich Switzerland
Anne-Marie Fouilliart THALSE Communications France
Simon Thabuteau THALSE Communications France
Luca Cristoforetti Fondazione Bruno Kessler Italy
Christian Zieger Fondazione Bruno Kessler Italy
Francesco Nesta Fondazione Bruno Kessler Italy
Mangesh Chitnis Scuola Superiore Sant'Anna Italy
Francesco Vitullo Università di Pisa Italy
Simone Secchi Università di Cagliari Italy
Paolo Meloni Università di Cagliari Italy
Ferruccio Bettarelli Leaff Engineering Italy
Ben Altieri ATMEL Roma Italy
Daniele Teti "Sapienza” Università di Roma Italy
Andrea Biagioni INFN Roma Italy
Francesco Simula INFN Roma Italy


CASTNESS08 SOCIAL DINNER, 15th evening

In a nice atmosphere, you could exchange impression about the event, the topics discussed or maybe just simply relax at the social dinner, enjoying good food and wine.

The social dinner will cost ~*40Euro/p to be payed (cash)at the CASTNESS registration*, the 15th in the morning.

After payment you will receive a voucher, and at the restaurant you will get a receipt at your name and, of course, your dinner!

If you would like to be part of the social dinner, we would appreciate if you could send us a confirmation at infocastness@roma1.infn.it.

Private Zone
navigation (public zone)
Project Partners