Personal tools
Views
From Euretile
Jump to: navigation, search

Contents

EURETILE Publications / Posters

Joint Papers (2013-2015)

  • P. S. Paolucci, A. Biagioni, L. G. Murillo, F. Rousseau, L. Schor, L. Tosoratto, I. Bacivarov, R. L. Buecs, C. Deschamps, A. El-Antably, R. Ammendola, N. Fournel, O. Frezza, R. Leupers, F. Lo Cicero, A. Lonardo, M. Martinelli, E. Pastorelli, D. Rai, D. Rossetti, F. Simula, L. Thiele, P. Vicini, J. H. Weinstock, "Dynamic many-process applications on many-tile embedded systems and HPC clusters: The EURETILE programming environment and execution platforms", Journal of Systems Architecture, Available online 24 November 2015, ISSN 1383-7621, http://dx.doi.org/10.1016/j.sysarc.2015.11.008.
  • L. Schor, I. Bacivarov, L. G. Murillo, P. S. Paolucci, F. Rousseau, A. El Antably, R. Buecs, N. Fournel, R. Leupers, D. Rai, L. Thiele, L. Tosoratto, P. Vicini, and J. Weinstock,"EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems", Parallel and Distributed Processing with Applications (ISPA), 2014 IEEE International Symposium on, Milan, Italy, Aug. 2014 http://dx.doi.org/10.1109/ISPA.2014.32.
  • J. H. Weinstock,et al., "Time-Decoupled Parallel SystemC Simulation", in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2014, Dresden, Germany http://dx.doi.org/10.7873/DATE.2014.204
  • C. Schumacher, et al., "legaSCi: Legacy SystemC Model Integration into Parallel Simulators", ACM Transactions on Embedded Computing Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems. http://dx.doi.org/10.1109/IPDPSW.2013.34
  • P. S. Paolucci, et al., "EURETILE D7.3 - Dynamic DAL benchmark coding, measurements on MPI version of DPSNN-STDP (distributed plastic spiking neural net) and improvements to other DAL codes", (Aug 2014), arXiv:1408.4587 [cs.DC], http://arxiv.org/abs/1408.4587
  • Paolucci, P.S., Bacivarov, I., Goossens, G., Leupers, R., Rousseau, F., Schumacher, C., Thiele, L., Vicini, P., "EURETILE 2010-2012 summary: first three years of activity of the European Reference Tiled Experiment", (2013), arXiv:1305.1459 [cs.DC] , http://arxiv.org/abs/1305.1459 - then published as ISBN: 978-88-908488-0-3 (2013), http://dx.doi.org/10.12837/2013T01

ETHZ

2014

  • A. Gomez, L. Schor, P. Kumar, and L. Thiele: "SF3P: A Framework to Explore and Prototype Hierarchical Compositions of Real-Time Schedulers", Proc. International Symposium on Rapid System Prototyping (RSP), New Delhi, October 2014. http://dx.doi.org/10.1109/RSP.2014.6966685
  • L. Schor, I. Bacivarov, H. Yang, and L. Thiele: "AdaPNet: Adapting Process Networks in Response to Resource Variations", Proc. International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), New Delhi, India, October 2014 http://dx.doi.org/10.1145/2656106.2656112
  • P. Kumar and L. Thiele: "Worst-Case Guarantees on a Processor with Temperature-based Feedback Control of Speed", ACM Trans. Embed. Comput. Syst. 13, 4s, Article 122, July 2014 http://dx.doi.org/10.1145/2584611
  • D. Rai, P. Huang, N. Stoimenov, and L. Thiele: "An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor". Proc. Design Automation Conference (DAC), San Francisco, CA, USA, June 2014 http://dx.doi.org/10.1145/2593069.2593085
  • S.-H. Kang, H. Yang, S. Kim, I. Bacivarov, S. Ha, and L. Thiele: "Static Mapping of Mixed-Critical Applications for Fault-Tolerant MPSoCs", Proc. Design Automation Conference (DAC), pages 31:1-31:6, San Francisco, CA, USA, June 2014. http://dx.doi.org/10.1145/2593069.2593221
  • S.-H. Kang, H. Yang, S. Kim, I. Bacivarov, S. Ha, and L. Thiele, "Reliability-Aware Mapping Optimization of Multi-Core Systems with Mixed-Criticality," Proc. IEEE/ACM Design Automation and Test in Europe (DATE), pages 327:1-327:4, 2014 http://dx.doi.org/10.7873/DATE.2014.340
  • L. Schor: "Programming Framework for Reliable and Efficient Embedded Many-Core Systems", PhD Thesis, ETH Zurich, October 2014.

2013

  • H. Yang, I. Bacivarov, D. Rai, J.-J. Chen, and L. Thiele: Real-Time Worst-Case Temperature Analysis with Temperature-Dependent Parameters. Real-Time Systems. Volume 49, Issue 6, p. 730-762, November 2013 http://dx.doi.org/10.1007/s11241-013-9188-y.
  • L. Schor, A. Tretter, T. Scherer and L. Thiele. Exploiting the Parallelism of Heterogeneous Systems using Dataflow Graphs on Top of OpenCL. Proc. IEEE Symposium on Embedded Systems for Real-time Multimedia (ESTIMedia), Montreal, Canada, p. 41-50, October 2013 http://dx.doi.org/10.1109/ESTIMedia.2013.6704502
  • L. Schor, H. Yang, I. Bacivarov and L. Thiele. Expandable Process Networks to Efficiently Specify and Explore Task, Data, and Pipeline Parallelism. Proc. International Conference on Compilers Architecture and Synthesis for Embedded Systems (CASES), Montreal, Canada, Oct. 2013 http://dl.acm.org/citation.cfm?id=2555729.2555734
  • L. Schor, I. Bacivarov, H. Yang and L. Thiele. Efficient Worst-Case Temperature Evaluation for Thermal-Aware Assignment of Real-Time Applications on MPSoCs. Journal of Electronic Testing: Theory and Applications. Volume 29, Issue 4, p. 521-535, August 2013 http://dx.doi.org/10.1007/s10836-013-5397-5
  • L. Schor, D. Rai, H. Yang, I. Bacivarov and L. Thiele. Reliable and Efficient Execution of Multiple Streaming Applications on Intel's SCC Processor. Proc. Workshop on Runtime and Operating Systems for the Many-core Era (ROME), Aachen, Germany, August 2013 http://doi.org/10.1007/978-3-642-54420-0_77
  • D. Rai, L. Schor, N. Stoimenov, I. Bacivarov and L.Thiele. Designing Applications with Predictable Runtime Characteristics for the Baremetal Intel SCC. Proc. Workshop on Runtime and Operating Systems for the Many-core Era (ROME), Aachen, Germany, August 2013 http://doi.org/10.1007/978-3-642-54420-0_76
  • D. Rai, L. Schor, N. Stoimenov and L. Thiele. Distributed Stable States for Process Networks - Algorithm, Analysis, and Experiments on the Intel SCC. Proceedings of the 50th Annual Design Automation Conference, Austin, TX, USA, p. 167:1--167:10, June 2013 [[1]].
  • L. Schor, H. Yang, I. Bacivarov, D. Rai and L. Thiele. Distributed Application Layer - Adaptive Mapping of Multiple Streaming Applications onto On-Chip Many-Core Systems (Poster). Joint Switzerland-Korea Symposium 2013, May 2013 [[2]].
  • L. Thiele, L. Schor, I. Bacivarov, and H. Yang. Predictability for Timing and Temperature in Multiprocessor System-on-Chip Platforms. ACM Transactions in Embedded Computing Systems (TECS), Volume 12, Mar. 2013 http://dx.doi.org/10.1145/2435227.2435244
  • P. Kumar, D. Chokshi, and L. Thiele. A Satisfiability Approach to Speed Assignment for Distributed Real-Time Systems. Proc. Design, Automation & Test in Europe Conference (DATE), Grenoble, France, Mar. 2013 http://doi.org/10.7873/DATE.2013.160

2012

  • P. Kumar, and L. Thiele. Behavioural Composition: Constructively Built Server Algorithms. Proc. 5th Workshop on Compositional Theory and Technology for Real-Time Embedded Systems, San Juan, Puerto Rico, p. 9-12, Dec. 2012.
  • P. Kumar and L. Thiele. Quantifying the Effect of Rare Timing Events with Settling-Time and Overshoot. Proc. IEEE Real-Time Systems Symposium (RTSS), San Juan, Puerto Rico, p. 149-160, Dec. 2012.
  • S.-H. Kang, H. Yang, L. Schor, I. Bacivarov, S. Ha, and L. Thiele. Multi-Objective Mapping Optimization via Problem Decomposition for Many-Core Systems. Proc. IEEE Symposium on Embedded Systems for Real-Time Multimedia (ESTIMedia), Tampere, Finland, p. 28-37, Oct. 2012.
  • L. Schor, I. Bacivarov, D. Rai, H. Yang, S.-H. Kang, and L. Thiele. Scenario-Based Design Flow for Mapping Streaming Applications onto On-Chip Many-Core Systems. Proc. Int'l Conf. on Compilers Architecture and Synthesis for Embedded Systems (CASES), Tampere, Finland, p. 71-80, Oct. 2012.
  • D. Rai, H. Yang, I. Bacivarov, and L. Thiele. Power Agnostic Technique for Efficient Temperature Estimation of Multicore Embedded Systems. Proc. Int'l Conf. on Compilers Architecture and Synthesis for Embedded Systems (CASES), Tampere, Finland, p. 61-70, Oct. 2012.
  • L. Schor, H. Yang, I. Bacivarov, and L. Thiele. Thermal-Aware Task Assignment for Real-Time Applications on Multi-Core Systems. Proc. Int'l Symposium on Formal Methods for Components and Objects (FMCO) 2011, Turin, Italy, Volume 7542 of LNCS, p. 294-313, Oct. 2012.
  • L. Schor, H. Yang, I. Bacivarov, and L. Thiele. Worst-Case Temperature Analysis for Different Resource Models. IET Circuits, Devices & Systems, Volume 6, Issue 5, p. 297-307, Sep. 2012.
  • K. Huang, W. Haid, I. Bacivarov, M. Keller, L. Thiele. Embedding Formal Performance Analysis into the Design Cycle of MPSoCs for Real-time Streaming Applications. ACM Transactions in Embedded Computing Systems (TECS Journal), ACM, Volume 11, Issue 1, p. 8:1-8:23, 2012.
  • L. Schor, I. Bacivarov, H. Yang, and L. Thiele. Fast Worst-Case Peak Temperature Evaluation for Real-Time Applications on Multi-Core Systems. Proc. IEEE Latin American Test Workshop (LATW), Quito, Ecuador, p. 1-6, Apr. 2012.
  • L. Schor, I. Bacivarov, H. Yang, and L. Thiele. Worst-Case Temperature Guarantees for Real-Time Applications on Multi-Core Systems. Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Beijing, China, p. 87-96, Apr. 2012.
  • P. Kumar and L. Thiele. Timing Analysis on a Processor with Temperature-Controlled Speed Scaling. Proc. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), Beijing, China, p. 77-86, Apr. 2012.
  • I. Bacivarov, I. Belaid, A. Biagioni, A. El Antably, N. Fournel, O. Frezza, J. Jovic, R. Leupers, F. Lo Cicero, A. Lonardo, L. Murillo, P.S. Paolucci, D. Rai, D. Rossetti, F. Rousseau, L. Schor, C. Schumacher, F. Simula, L. Thiele, L. Tosoratto, P. Vicini, H. Yang – “DAL: Programming Efficient and Fault-Tolerant Applications for Many-Core Systems” - Poster at HIPEAC12 - Jan 23-25, 2012 Paris, France

2011

  • P. Kumar, J.-J. Chen, and L. Thiele. Demand Bound Server: Generalized Resource Reservation for Hard Real-Time Systems. Proc. Int'l Conference on Embedded Software (EMSOFT), pages 233-242, Oct. 2011.
  • L. Schor, H. Yang, I. Bacivarov, and L. Thiele. Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. Proc. Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Lecture Notes on Computer Science (LNCS), Springer, Vol. 6951, pages 288-297, Sep. 2011.
  • P. Kumar, J.-J. Chen, L. Thiele, A. Schranzhofer, and G. C. Buttazzo. Real-Time Analysis of Servers for General Job Arrivals. Proc. Intl. Conf. on Embedded and Real-Time Computing Systems and Applications (RTCSA), pages 251-258, Aug. 2011.
  • L. Thiele, L. Schor, H. Yang, and I. Bacivarov. Thermal-Aware System Analysis and Software Synthesis for Embedded Multi-Processors. Proc. Design Automation Conference (DAC), pages 268-273, Jun. 2011.
  • D. Rai, H. Yang, I. Bacivarov, JJ. Chen, L. Thiele. Worst-Case Temperature Analysis for Real-Time Systems. In Proceedings of Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011. http://dx.doi.org/10.1109/DATE.2011.5763104
  • S. Perathoner, K. Lampka, L. Thiele. Composing Heterogeneous Components for System-wide Performance Analysis. In Proceedings of Design, Automation and Test in Europe (DATE), Grenoble, France, March 2011 (invited paper).
  • I. Bacivarov, H. Yang, L. Schor, D. Rai, S. Jha, L. Thiele, Poster: Distributed Application Layer - Towards Efficient and Reliable Programming of Many-Tile Architectures. Design, Automation and Test in Europe (DATE) Friday Workshop, Grenoble, France, March 2011.
  • K. Huang, L. Santinelli, JJ. Chen, L. Thiele, and G. C. Buttazzo. Applying Real-Time Interface and Calculus for Dynamic Power Management in Hard Real-Time Systems. Real-Time Systems Journal, Springer Netherlands, Vol. 47, No. 2, pages 163-193, Mar. 2011.

2010

  • A. Schranzhofer, JJ. Chen, L. Thiele. Dynamic Power-Aware Mapping of Applications onto Heterogeneous MPSoC Platforms. IEEE Transactions on Industrial Informatics, IEEE, Vol. 6, No. 4, pages 692 -707, November, 2010.

RWTH

2015

  • please update

2014

  • please check 2014 list for completeness
  • L. G. Murillo, R. Buecs, R., D. Hincapie, R. Leupers, and G. Ascheid, SWAT: Assertion-based Debugging of Concurrency Issues at System Level, in ASP-DAC‘15, Chiba/Tokyo, Japan, Jan. 2015, (accepted for publication)
  • L. G. Murillo, R. Buecs, D. Hincapie, R. Leupers and G. Ascheid, Assertion-based Debugging of Concurrency Issues in Many-core Systems across HW/SW Boundaries, in DAC‘14 Work in Progress Session (WIP), June 2014, San Francisco, USA [[3]]
  • L. G. Murillo, S. Wawroschek, J. Castrillon, R. Leupers and G. Ascheid: "Automatic Detection of Concurrency Bugs through Event Ordering Constraints", in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2014, Dresden, Germany [[4]]
  • J. H. Weinstock, C. Schumacher, R. Leupers, G. Ascheid and L. Tosoratto: "Time-Decoupled Parallel SystemC Simulation", in Proceedings of the Conference on Design, Automation & Test in Europe (DATE), 2014, Dresden, Germany [[5]]

2013

  • C. Schumacher, J. H. Weinstock, R. Leupers, G. Ascheid, L. Tosoratto, A. Lonardo, D. Petras, A. Hoffmann: "legaSCi: Legacy SystemC Model Integration into Parallel Simulators", ACM Transactions on Embedded Computing Systems, Special Issue on Virtual Prototyping of Parallel and Embedded Systems. (to appear)
  • J. H. Weinstock, C. Schumacher, R. Leupers and G. Ascheid: "SCandal: SystemC Analysis for Nondeterminism Anomalies", in Models, Methods, and Tools for Complex Chip Design (Haase, J., ed.) vol. 265 of Lecture Notes in Electrical Engineering. Springer, 2013. [[6]]
  • C. Schumacher, J. H. Weinstock, R. Leupers, G. Ascheid, L. Tosoratto, A. Lonardo, D. Petras, A. Hoffmann. “legaSCi: Legacy SystemC Model Integration into Parallel SystemC Simulators”. 1st Workshop on Virtual Prototyping of Parallel and Embedded Systems (ViPES), 2013, Boston, USA. [[7]]

2012

  • C. Schumacher, J. H. Weinstock, R. Leupers and G. Ascheid. Cause and effect of nondeterministic behavior in sequential and parallel SystemC simulators. IEEE International High Level Design Validation and Test Workshop (HLDVT'12). Nov 2012, Huntington Beach (California-USA). [[8]]
  • C. Schumacher, J. H. Weinstock, R. Leupers and G. Ascheid: Scandal: SystemC Analysis for NonDeterminism AnomaLies. Forum on Specification and Design Languages (FDL '12), Sep 2012, Vienna (Austria) [[9]]
  • L. G. Murillo, J. Harnath, R. Leupers and G. Ascheid. Scalable and Retargetable Debugger Architecture for Heterogeneous MPSoCs. System, Software, SoC and Silicon Debug Conference (S4D '12), Sep 2012, Vienna (Austria) [[10]]
  • L. G. Murillo, J. Eusse, J. Jovic, S. Yakoushkin, R. Leupers and G. Ascheid: Synchronization for Hybrid MPSoC Full-System Simulation. Design Automation Conference (DAC '12), Jun 2012, San Francisco (USA) [[11]]
  • R. Leupers, F. Schirrmeister, G. Martin, T. Kogel, R. Plyaskin, A. Herkersdorf and M. Vaupel. Virtual platforms: Breaking new grounds (More Real Value for Virtual Platforms). Design, Automation and Test in Europe (DATE '12), Mar 2012, Dresden (Germany) [[12]]
  • J. Jovic, S. Yakoushkin, L. G. Murillo, J. Eusse, R. Leupers and G. Ascheid: Hybrid Simulation for Extensible Processor Cores. Design, Automation and Test in Europe (DATE '12), Mar 2012, Dresden (Germany) [[13]]

2011

  • S. Kraemer, R. Leupers, D. Petras, T. Philipp, A. Hoffmann. Checkpointing SystemC-Based Virtual Platforms. International Journal of Embedded and Real-Time Communication Systems (IJERTCS), vol. 2, no. 4, 2011 [[14]]
  • L. G. Murillo, W. Zhou, J. Eusse, R. Leupers, G. Ascheid. Debugging Concurrent MPSoC Software with Bug Pattern Descriptions. System, Software, SoC and Silicon Debug Conference (S4D '11), Oct 2011, Munich (Germany) [[15]]
  • R. Leupers, G. Martin, N. Topham, L. Eeckhout, F. Schirrmeister, X. Chen: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores. Design Automation & Test in Europe (DATE), Mar 2011, Grenoble (France) [[16]]
  • J. Castrillon, A. Shah, L. G. Murillo, R. Leupers, G. Ascheid. Backend for Virtual Platforms with Hardware Scheduler in the MAPS Framework. 2nd IEEE Latin America Symp. on Circuits and Systems, Feb 2011, Bogota (Colombia) [[17]]
  • S. Kraemer, Design and analysis of efficient MPSoC simulation techniques, dissertation, 2011, Aachen, Germany [[18]]

2010

  • C. Schumacher, R. Leupers, D. Petras and A. Hoffmann. parSC: Synchronous Parallel SystemC Simulation on Multi-Core Host Architectures. In Proceedings of CODES/ISSS '10, October, 2010, Scottsdale, Arizona, USA [[19]]

INFN

2015

  • P.S. Paolucci et al., "Dynamic Many-process Applications on Many-tile Embedded Systems and HPC Clusters: the EURETILE programming environment and execution platforms", Journal of Systems Architecture, Available online 24 November 2015, ISSN 1383-7621, http://dx.doi.org/10.1016/j.sysarc.2015.11.008.
  • E. Pastorelli, et al., "Scaling to 1024 software processes and hardware cores of the distributed simulation of a spiking neural network including up to 20G synapses", (2015) arXiv:1511.09325, http://arxiv.org/abs/1511.09325
  • E. Pastorelli, et al., "Impact of exponential long range and Gaussian short range lateral connectivity on the distributed simulation of neural networks including up to 30 billion synapses", (2015) arXiv:1512.05264, http://arxiv.org/abs/1512.05264
  • P.S. Paolucci, et al. "Power, Energy and Speed of Embedded and Server Multi-Cores applied to Distributed Simulation of Spiking Neural Networks: ARM in NVIDIA Tegra vs Intel Xeon quad-cores", (2015) http://arxiv.org/abs/arXiv:1505.03015
  • R. Ammendola et al., "ASIP acceleration for virtual-to-physical address translation on RDMA-enabled FPGA-based network interfaces", Future Generation Computer Systems, vol. 53 (2015) pag. 109-118, http://dx.doi.org/10.1016/j.future.2014.12.012

2014

  • 2014 list to be checked
  • A. Lonardo et al., "A FPGA-based Network Interface Card with GPUDirect enabling real-time GPU computing in HEP experiments", GPU Computing in High-Energy Physics (GPUHEP2014) : Pisa, Italy, September 2014, http://dx.doi.org/10.3204/DESY-PROC-2014-05/16
  • L. Schor et al., "EURETILE Design Flow: Dynamic and Fault Tolerant Mapping of Multiple Applications onto Many-Tile Systems", Parallel and Distributed Processing with Applications (ISPA), 2014 IEEE Int. Symp. on, (2014) pag. 182-189, http://dx.doi.org/10.1109/ISPA.2014.32
  • R. Ammendola et al., "LO-FA-MO: Fault Detection and Systemic Awareness for the QUonG Computing System," in Reliable Distributed Systems (SRDS), 2014 IEEE 33rd International Symposium on, pp.265-270, http://dx.doi.org/10.1109/SRDS.2014.33
  • G. Lamanna et al., "GPUs for real-time processing in HEP trigger systems", Journal of Physics: Conference Series, vol. 513, (2014), International Conference on Computing in High Energy and Nuclear Physics (CHEP) 2013, http://dx.doi.org/10.1088/1742-6596/513/1/012017
  • R. Ammendola et al., “Analysis of performance improvements for host and GPU interface of the APENet+ 3D Torus network“, Journal of Physics: Conference Series, vol. 513, (2014), Workshop on Advanced Computing & Analysis Techniques in Physics Research (ACAT) 2013, http://dx.doi.org/10.1088/1742-6596/523/1/012013
  • R. Ammendola et al., "NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs“, in JINST, Journal of Instrumentation, vol. 9 (2014), Proceedings of Topical Workshop on Electronics for Particle Physics (TWEPP) 2013, IOP Publishing, 2013, http://dx.doi.org/10.1088/1748-0221/9/02/C02023.
  • A. Lonardo, et al., "NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features", preprint arXiv:1406.3568 [physics.ins-det].
  • A. Biagioni, et al., "Evolution of FPGA-based network acceleration for GPUs", poster at the conference Perspectives of GPU Computing in Physics and Astrophysics, Rome, Italy, September 15-17, 2014
  • A. Biagioni, et al., "Development of a GPU aware NIC: from HPC to HEP experiments", poster at the conference (GTC) GPU Technology Conference, March 24-26, 2013 - San Jose (California)
  • P.S. Paolucci, et al., "Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a mini app benchmark", Poster at the Workshop 'Dagli atomi al cervello', Politecnico di Milano, 27 Jan 2014

2013

  • R. Ammendola, et al. “GPU peer-to-PeerTechniques Applied to a Cluster Interconnect” in Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2013 IEEE 27th International, pp. 806–815, 2013, http://dx.doi.org/10.1109/IPDPSW.2013.128
  • R. Ammendola, et al. “APEnet+ 34 Gbps data transmission system and custom transmission logic” in JINST, Journal of Instrumentation, Proceedings of Topical Workshop on Electronics for Particle Physics (TWEPP) 2013, IOP Publishing, 2013. http://dx.doi.org/10.1088/1748-0221/8/12/C12022
  • R. Ammendola, et al., “Virtual-to-Physical Address Translation for an FPGA-based Interconnect with Host and GPU Remote DMA Capabilities” in Field-Programmable Technology (FPT), 2013 International Conference on, 2013. http://dx.doi.org/FPT.2013.6718331
  • R. Ammendola, et al., “Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems“, Journal of Physics: Conference Series, International Conference on Computing in High Energy and Nuclear Physics (CHEP) 2013, http://dx.doi.org/10.1088/1742-6596/513/5/052002
  • R. Ammendola, et al., “NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems“ , Journal of Physics: Conference Series, International Conference on Computing in High Energy and Nuclear Physics (CHEP) 2013, http://dx.doi.org/10.1088/1742-6596/513/1/012018
  • R. Ammendola, et al. “The GAP Project - GPU for Realtime Applications in High Energy Physics and Medical Imaging“, IEEE Xplore, Nuclear Science Symposium and Medical Imaging Conference workshop (NSS/MIC) 2013, http://dx.doi.org/10.1109/NSSMIC.2013.6829757.
  • R. Ammendola, et al., “Design and implementation of a modular, low latency, fault-aware, FPGA-based Network Interface", IEEE Xplore, track on International Conference on Reconfigurable Computing and FPGAs (ReConFig) 2013, http://dx.doi.org/10.1109/ReConFig.2013.6732275.
  • R. Ammendola, et al., “Mutual Watch-dog Networking’: Distributed Awareness of Faults and Critical Events in Petascale/Exascale systems” arXiv:1307.0433, July 2013.
  • P. S. Paolucci, et al. , “Distributed simulation of polychronous and plastic spiking neural networks: strong and weak scaling of a representative mini-application benchmark executed on a small-scale commodity cluster“ (2013) arXiv:1310.8478
  • R. Ammendola, et al., "A heterogeneous many-core platform for experiments on scalable custom interconnects and management of fault and critical events, applied to many-process applications: Vol. II", 2012 technical report - arXiv preprint arXiv:1307.1270

2012

  • Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini. APEnet+: a 3-D Torus network optimized for GPU-based HPC Systems. New York, NY. Proceedings on 2012 J. Phys.: Conf. Ser. 396 042059 doi:10.1088/1742-6596/396/4/042059 [[20]]. (CHEP 2012).
  • R. Ammendola, A. Biagioni, O. Frezza, A. Lonardo, F. Lo Cicero, P. S. Paolucci, D. Rossetti, A. Salamon, F. Simula, L. Tosoratto, P. Vicini. A 34 Gbps Data Transmission System with FPGAs Embedded Transceivers and QSFP plus Modules. 2012 IEEE NUCLEAR SCIENCE SYMPOSIUM AND MEDICAL IMAGING CONFERENCE RECORD (NSS/MIC). Book Series: IEEE Nuclear Science Symposium Conference Record. Pages: 872-876. Published: 2012.
  • R Ammendola, A Biagioni, O Frezza, F Lo Cicero, A Lonardo, PS Paolucci, D Rossetti, F Simula, L Tosoratto, P Vicini. APEnet+: a 3D Torus network optimized for GPU-based HPC Systems. Journal of Physics: Conference Series - 396 042059 doi:10.1088/1742-6596/396/4/042059 CHEP 2012 proceedings [[21]]
  • S. Amerio, R. Ammendola, A. Biagioni, D. Bastieri, D. Benjamin, O. Frezza, S. Gelain, W. Ketchum, Y. K. Kim, F. Lo Cicero, A. Lonardo, T. Liu, D. Lucchesi, P. S. Paolucci, S. Poprocki, D. Rossetti, F. Simula, L. Tosoratto, G. Urso, P. Vicini, and P. Wittich. Applications of GPUs to online track reconstruction in HEP experiments. - NSS-MIC 2012 Proceedings DOI: 10.1109/NSSMIC.2012.6551422
  • I. Bacivarov, I. Belaid, A. Biagioni, A. El Antably, N. Fournel, O. Frezza, W. Geurts, G. Goossens, J. Jovic, R. Leupers, F. Lo Cicero, A. Lonardo, L. Murillo, P. S. Paolucci, D. Rai, D. Rossetti, F. Rousseau, L. Schor, C. Schumacher, F. Simula, L. Thiele, L. Tosoratto, P. Vicini and H. Yang. EURETILE: Unified Networking Infrastructure for Embedded and HPC many-tile platforms. Poster at HIPEAC12. Jan 2012 Paris, France [[22]]
  • P. S. Paolucci. Brain Simulation Benchmark: Inspiring and benchmarking the scalability and fault-tolerance of future many-tile systems. Poster at HIPEAC12. Jan 2012 Paris, France, [[23]]

2011

  • Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti, Francesco Simula, Laura Tosoratto, Piero Vicini. QUonG: A GPU-based HPC System Dedicated to LQCD Computing. Application Accelerators in High-Performance Computing, Symposium on, pp. 113-122, 2011 Symposium on Application Accelerators in High-Performance Computing, (SAAHPC 2011) http://doi.ieeecomputersociety.org/10.1109/SAAHPC.2011.15
  • Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Stanislao Paolucci, Davide Rossetti,Francesco Simula, Laura Tosoratto and Piero Vicini. APEnet+ project status. - Proceedings of XXIX International Symposium on Lattice Field Theory (Lattice 2011). July 10-16, 2011. Squaw Valley, Lake Tahoe, CA http://pos.sissa.it/archive/conferences/139/045/Lattice%202011_045.pdf

2010

  • Pier Stanislao Paolucci. FP7 EURETILE Project: EUropean REference TILed architecture Experiment. HipeacInfo, Quarterly Newsletter, Number 24, page 11, October 2010 (http://www.Hipeac.net/newsletter) File:PaolucciEuretileHipeacInfo24October2010.pdf
  • Roberto Ammendola, Andrea Biagioni, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Pier Paolucci, Roberto Petronzio, Davide Rossetti, Andrea Salamon, Gaetano Salina, Francesco Simula, Nazario Tantalo, Laura Tosoratto, Piero Vicini. APEnet+: a 3D toroidal network enabling Petaflops scale Lattice QCD simulations on commodity clusters. Proceedings of Science, PoS(Lattice 2010)022, http://pos.sissa.it/archive/conferences/105/022/Lattice%202010_022.pdf, Proceedings of The XXVIII International Symposium on Lattice Field Theory, Lattice 2010. arXiv:1012.0253 [hep-lat].
  • R. Ammendola, A. Biagioni, O. Frezza, F. Lo Cicero, A. Lonardo, P.S. Paolucci, D. Rossetti, A. Salamon, G. Salina, F. Simula, L. Tosoratto, P. Vicini. apeNET+: High Bandwidth 3D Torus Direct Network for PetaFLOPS Scale Commodity Clusters. 2011 J. Phys.: Conf. Ser. 331 052029 doi:10.1088/1742-6596/331/5/052029, Proceedings of International Conference on Computing in High Energy and Nuclear Physics (CHEP 2010), October 2010, Taipei, Taiwan
  • R. Ammendola, A. Biagioni, O. Frezza, F. Lo Cicero, A. Lonardo, P.S. Paolucci, D. Rossetti, A. Salamon, G. Salina, F. Simula, L. Tosoratto, P. Vicini. Mastering multi-GPU computing on a torus network. GPU Technology Conference 2010 (GTC2010). http://www.nvidia.com/content/GTC/posters/2010/I09-Mastering-Multi-GPU-Computing-on-a-Torus-Networki.pdf (poster)
  • R. Ammendola, A. Biagioni, G. Chiodi, O. Frezza, F. Lo Cicero, A. Lonardo, R. Lunadei, P.S. Paolucci, D. Rossetti, A. Salamon, G. Salina, F. Simula, L. Tosoratto and P. Vicini. High speed data transfer with FPGAs and QSFP+ modules. JINST 5 C12019 doi:10.1088/1748-0221/5/12/C12019
  • Ammendola, R.; Biagioni, A.; Chiodi, G.; Frezza, O.; Cicero, F.L.; Lonardo, A.; Lunadei, R.; Paolucci, P.; Rossetti, D.; Salamon, A.; Salina, G.; Simula, F.; Tosoratto, L.; Vicini, P., High speed data transfer with FPGAs and QSFP+modules. Nuclear Science Symposium Conference Record (NSS/MIC), 2010 IEEE , vol., no., pp.1323,1325, Oct. 30 2010-Nov. 6 2010 doi: 10.1109/NSSMIC.2010.5873983

TIMA

2015

  • please update

2014

  • please check 2014 list for completeness
  • A. ElAntably, N. Fournel, F. Rousseau, "Lightweight task migration in embedded multi-tiled architectures using task code replication", Rapid System Prototyping symposium RSP symposium), part of the Embedded System week (ESWeek) 2014, Greater Noida, India, 16 and 17th of Oct. 2014.
  • H. Chen, G. Godet-Bar, F. Rousseau, F. Pétrot, Device Driver Generation Targeting Multiple Operating Systems Using a Model-driven Methodology, Rapid System Prototyping symposium RSP symposium), part of the Embedded System week (ESWeek) 2014, Greater Noida, India, 16 and 17th of Oct. 2014.

2013

  • M. Jaber, A. Chagoya-Garzon, F. Rousseau, From System Model Formalization Towards Correct and Efficient HW/SW Design, DTIS Conference , March 2013, pp. 88 – 94, Abu Dabi, UAE.

2012

  • A. Chagoya-Garzon, F. Rousseau, F. Pétrot. Multi-Device Driver Synthesis Flow for Heterogeneous Hierarchical Systems. Euromicro Conference on Digital System Design, Sept 2012, pp. 389 – 396, Izmir, Turkey.
  • Ashraf Elantably, Frédéric Rousseau. Task migration in multi-tiled MPSoC: Challenges, state-of-the-art and preliminary solutions. Journée National du Réseau Doctoral en Microélectronique, Marseille, France, June 2012, Poster and 4 pages paper (in English).

2011

  • A. Chagoya-Garzon, N. Poste, F. Rousseau. Semi-Automation of Configuration Files Generation for Heterogeneous Multi-Tile Systems, Computer Software and Application Conference (COMPSAC 2011), Munich, Germany, 18-21 July 2011.
  • H. Chen, G. Godet-Bar, F. Rousseau, F. Petrot. Me3D: A Model-driven Methodology expediting Embedded Device Driver Development, International Symposium on Rapid System Prototyping (IEEE RSP 2011), pp. 171-177, May 2011, Karlshrue, Germany.

A few presentations of project results

ETHZ

2014

  • Panel discussion ‐ Self‐Adaptive Computing Systems: myths and successes, what to expect in the next 10 years. Organizers: Marco D. Santambrogio, Politecnico di Milano, Italy, Hank Hoffmann, University of Chicago, IL, USA; Panelists: Iuliana Bacivarov - ETH Zürich, Switzerland; Ayse K. Coskun - Boston Univ., Boston, MA; Steven Hofmeyr - Lawrence Berkeley National Lab, Berkeley, CA; Gianluca Durelli - Politecnico di Milano, Italy; Oliver Pell - Univ. of California, Berkeley; Hank Hoffman - Univ. of Chicago, IL; Alessandro Nacci - Politecnico di Milano, Italy; Christian Pilato - Columbia Univ., New York, NY.
  • Iuliana Bacivarov, AdaPNet Runtime System: Adapting Process Networks to Resource Variations. CHANGE Workshop co-located with Parallel and Pervasive Computing Week 2014, 25 August 2014, Milan, Italy.
  • Iuliana Bacivarov, Adapting Process Networks to Dynamic Resource Changes – the AdaPNet Approach. CHANGE Workshop co-located with 51st Design Automation Conference (DAC), 1 June 2014, San Francisco, CA, USA.
  • Iuliana Bacivarov, Mastering the Design of Modern Complex Distributed Systems. Public seminar at EPF Lausanne, 7 March 2014, Lausanne, Switzerland.

2013

  • Iuliana Bacivarov, How model-based design simplifies the debugging of many-core systems. 1st International Workshop on Multicore Application Debugging (MAD 2013). Nov. 2013, Munich, Germany.
  • Iuliana Bacivarov, Distributed Application Layer: mapping dynamic applications on many-core systems. CASTNESS'13. June 28th, 2013, Barcelona, Spain.
  • Iuliana Bacivarov, Distributed Application Layer - Run-time mapping of streaming applications on heterogeneous many-core systems. DAC CHANGE - Computing in Heterogeneous, Autonomous 'N' Goal-oriented Environments, June 2013, Austin, TX, USA.

2012

  • Iuliana Bacivarov, System-Level Thermal Aware Design of Real-Time Embedded Systems, Lecture at Design and Test Summer School 2012, Oct. 2012, Puebla, Mexico.
  • Iuliana Bacivarov, Distributed Application Layer: Scenario-Based Design Flow for Mapping Streaming Applications onto On-Chip Many-Core Systems, Invited talk at Thales Paris, Aug. 2012, Paris, France.
  • Iuliana Bacivarov, EU FP7 project EURETILE - EUropean REference TILed architecture Experiment (2010-2013): Distributed Application Layer, in Special Session on Ongoing EU Projects at ASAP 2012, Jul. 2012, Delft, Netherlands.
  • Iuliana Bacivarov, Distributed Application Layer: Efficient Programming of Reliable Many-Core Systems, Invited talk at TU Delft, Jun. 2012, Delft, Netherlands.
  • Iuliana Bacivarov, Distributed Application Layer: Mapping Dynamic Streaming Applications onto Many-Core Systems, Invited talk at Map2MPSoC/SCOPES, May 2012, Schloss Rheinfels, St. Goar, Germany.
  • Iuliana Bacivarov, Management of Process Network Dynamism in the Distributed Application Layer, CASTNESS 2012, Jan. 2012, Paris, France.

2011

  • Iuliana Bacivarov, Thermal-Aware Design of Real-Time Multi-Core Embedded Systems, Invited talk at Mapping Applications to MPSoCs, Jun. 2011.
  • Iuliana Bacivarov, Temperature Predictability in Multi-Core Real-Time Systems, Invited talk at DAC Workshop on Multiprocessor System-on-Chip for Cyber Physical Systems: Programmability, Run-Time Support, and Hardware Platforms for High Performance Embedded Applications, Jun. 2011.
  • Iuliana Bacivarov, Distributed Application Layer – Towards Seamless Programming of Many-Tile Architectures, CASTNESS 2011, 17 and 18 January 2011, Rome, Italy, http://euretile.roma1.infn.it/mediawiki/img_auth.php/8/88/EURETILE-2-IulianaBacivarov.pdf.

2010

  • Iuliana Bacivarov, Distributed Operation Layer: An Efficient and Predictable KPN-Based Design Flow, invited talk at Workshop on Compiler-Assisted System-On-Chip Assembly 2010, in conjunction with Embedded Systems Week, Scottsdale, AZ, US, October 2010, http://www12.cs.fau.de/ws/casa10.
  • Iuliana Bacivarov, Efficient Execution of Kahn Process Networks on CELL BE, invited talk at Summer School on Models for Embedded Signal Processing Systems at Lorentz Center, Leiden, Netherlands, 30 Aug - 3 Sep 2010, http://www.lorentzcenter.nl/lc/web/2010/427/presentations/Iuliana-cell.pdf.
  • Iuliana Bacivarov, Distributed Operation Layer: A Practical Perspective, tutorial at Summer School on Models for Embedded Signal Processing Systems at Lorentz Center, Leiden, Netherlands, 30 Aug - 3 Sep 2010, http://www.lorentzcenter.nl/lc/web/2010/427/presentations/Iuliana-demo.pdf.
  • Iuliana Bacivarov, Distributed Operation Layer: Efficient Design Space Exploration of Scalable MPSoC, invited talk at Combinatorial Optimization for Embedded System Design workshop 2010 in conjunction with CPAIOR2010, 7th International Conference on Integration of Artificial Intelligence and Operations Research techniques in Constraint Programming, Bologna, Italy, June 2010, http://www.artist-embedded.org/artist/Overview,2022.html.
  • Iuliana Bacivarov, invited talk at Efficient Execution of Kahn Process Networks on MPSoC, Mapping Applications to MPSoCs 2010, June 29-30, 2010, St. Goar, Germany, http://www.artist-embedded.org/artist/Program,1822.html.

RWTH

2014

  • L.G. Murillo. "System-level Debugging". Joint RWTH/Synopsys workshop, Nov 2014, Aachen, Germany
  • J. Weinstock. "Flexible Time-Decoupling for Electronic System Level Simulators". Joint RWTH/Synopsys workshop, Nov 2014, Aachen, Germany
  • L. G. Murillo. SW Debugging for Multi-tile Systems: The EURETILE Methodology and Tools. 2nd International Workshop on Multi-core Applications Debugging. HiPEAC Fall Computing Systems Week, October 2014, Athens, Greece.
  • R. Leupers. HiPEAC Workshop for New EU Member States. Zagreb (Croatia) and Ljubljana (Slovenia), Sept 2014
  • R. Leupers, L. G. Murillo. 2nd International Workshop on Multi-core Applications Debugging (co-organization with TU Munich and HiPEAC). October 2014, Athens, Greece.
  • R. Leupers. Joint Seminar RWTH/Kadir Has Univ., Jun 2014, Istanbul, Turkey
  • R. Leupers. Embedded Processor Design, course. Thai-German Graduate School (TGGS), Apr 2014, Bangkok, Thailand
  • J. Weinstock. "Time-Decoupled Parallel SystemC Simulation". DATE Conference, University Booth, Mar 2014, Dresden, Germany
  • J. Weinstock. GEMSCLAIM Bi-annual Meeting. "A Parallel GEMSCLAIM Simulator using Flexible Time-Decoupling", Feb 2014, Timisoara, Romania
  • R. Leupers. Academia to industry technology transfer and IP in domain of Computer Systems, HiPEAC Workshop, Feb 2014, Timisoara, Romania
  • R. Leupers. Embedded Processor Design, Block lecture ALaRI, Jan-Feb 2014, University of Lugano, Lugano, Switzerland
  • R. Leupers. TISU Workshop, Jan 2014, Vienna, Austria

2013

  • J. H. Weinstock. Time-decoupled Parallel SystemC Simulation. Joint RWTH/Synopsys Seminar. Dec 2013, Aachen, Germany.
  • L. G. Murillo. Simulation-based Concurrent Software Debugging. Joint RWTH/Synopsys Seminar. Dec 2013, Aachen, Germany.
  • L. G. Murillo. Automatic Exploration of SW Concurrency Bugs through Deterministic Behavior Control. 1st International Workshop on Multi-core Applications Debugging. November 2013, Munich, Germany.
  • R. Leupers, L. G. Murillo. 1st International Workshop on Multi-core Applications Debugging (co-organization with TU Munich). November 2013, Munich, Germany.
  • R. Leupers. Keynote at Sabanci Univ, Oct 2013, Istanbul, Turkey
  • R. Leupers. Two new Use Cases for Virtual Platforms. 13th International Forum on Embedded MPSoC and Multicore (MPSoC'13). July 2013, Otsu, Japan
  • J. H. Weinstock. The EURETILE Parallel Simulation Environment. CASTNESS'13, June 2013, Barcelona, Spain.
  • L. G. Murillo. Simulation-based MPSoC Software Debugging. Joint RWTH/TU Munich Research Seminar, May 2013, Munich, Germany.
  • R. Leupers. System-Level Design Technologies for Embedded Multicore Devices. HiPEAC workshop, Apr 2013, Sibiu, Romania
  • R. Leupers. HiPEAC boot at DATE'13, Mar 2013, Grenoble, France
  • R. Leupers. System-Level Design Technologies. Joint RWTH/Intel Lab seminar, Mar 2013, Aachen, Germany
  • R. Leupers. Embedded Processor Design, Block lecture ALaRI, Jan-Feb 2013, University of Lugano, Lugano, Switzerland.
  • R. Leupers (organizer). Programming Embedded Multiprocessor Systems: Application Code Mapping and Performance Estimation Technologies. Tutorial. 8th Asia and South Pacific Design Automation Conference (ASP-DAC), Jan 2013. Yokohama, Japan
  • R. Leupers. Joint RWTH/U Ghent Seminar, Jan 2013, Aachen, Germany
  • R. Leupers. Embedded Processor Design, course. Thai-German Graduate School (TGGS), Jan 2013, Bangkok, Thailand

2012

  • R. Leupers. Multicore Platform Design: Tackling a Grand Challenge in Embedded Computing. Keynote at the 15th Euromicro Conference on Digital System Design (DSD '12), Sep 2012, Izmir, Turkey
  • R. Leupers. Embedded Multicore Design Technologies: The Next Generation. Keynote at the IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP '12), Jul 2012, Delft, The Netherlands
  • R. Leupers. Design Technologies for Wireless Multiprocessor Systems-on-Chip, PhD course, University of Pisa, Jul 2012, Pisa, Italy
  • Christoph Schumacher. Virtual EURETILE Platform: a Platform for Many-tiled Systems Simulation. Joint RWTH/TU Poznan Seminar, May 2012, Poznan, Poland
  • R. Leupers (session chair). Workshop at DATE 2012: "Quo Vadis, Virtual Platforms? Challenges and Solutions for Today and Tomorrow". Mar 2012, Dresden, Germany
  • R. Leupers (organized by). Special session at DATE 2012: "Virtual Platforms: Breaking New Grounds". Mar 2012, Dresden, Germany
  • R. Leupers, H. Meyr. Embedded Processor Design, Block lecture ALaRI, Feb 2012, University of Lugano, Lugano, Switzerland
  • R. Leupers. What's hot on Embedded System Design. Keynote at the Embedded Technology Conference (ETC '12), Feb 2012, San Pedro, Costa Rica
  • Luis Murillo. Simulation-based software debugging in many-tile systems. CASTNESS 2012, January 26, 2012, Paris, France

2011

  • Juan Eusse. Hybrid Simulation Technology for Extensible Cores and Full System Simulation of Complex MPSoCs. Presentation at HiPEAC Computing Systems Week, Nov 2011, Barcelona, Spain
  • R. Leupers. SoC Design Research in the UMIC Excellence Cluster, Seminar, TU Berlin, Sep 2011, Berlin, Germany
  • S. Yakoushkin. Advanced Simulation Techniques, Joint RWTH/TU Tampere Seminar, June 2011, Tampere, Finland
  • R. Leupers (organized by). ICT Technology Transfer Workshop targeting Horizon 2020, Apr 2011, Brussels, Belgium
  • R. Leupers and G. Martin (organized by). Special session at DATE 2011: Virtual Manycore Platforms: Moving Towards 100+ Processor Cores, March 2011, Grenoble, France
  • R. Leupers, H. Meyr. Embedded Processor Design, Block lecture ALaRI, Feb 2011, University of Lugano, Lugano, Switzerland
  • Jovana Jovic, Simulation Challenges in the EURETILE Project, CASTNESS 2011, January 17-18, 2011, Rome, Italy

2010

  • Christoph Schumacher, Virtual Platform Technologies for Multi-core Platforms, UMIC Day, 19 October, 2010, RWTH Aachen, Germany
  • Rainer Leupers, HiPEAC Cluster Meeting (Design and Simulation Cluster), October 2010, Barcelona, Spain
  • Rainer Leupers, Design Technologies for Wireless Systems-On-Chip, Huawei ESL Symposium, September 2010, Shenzhen, People's Republic of China
  • Christoph Schumacher, Stefan Kraemer and Rainer Leupers, demonstration at DAC 2010 exhibition: parSC: parallel SystemC simulation, deterministic, accurate, fast, June 14-16, 2010, Anaheim, USA
  • Rainer Leupers, MPSoC Design for Wireless Multimedia, Tutorial, MIXDES, June 2010, Wroclaw, Poland
  • Stefan Kraemer, Advanced Simulation Techniques for Virtual Platforms, May 26, 2010, Imperial College London, London, United Kingdom
  • Rainer Leupers, Cool MPSoC Design, ASCI Winter School on Embedded Systems, March 2010, Soesterburg, Netherlands
  • Rainer Leupers, Embedded Procesor Design and Implementation, course in MSc in Embedded Systems track at ALaRI Institute, March 1-4, 2010, University of Lugano, Switzerland

INFN

2014

  • Roberto Ammendola, LO|FA|MO: Fault Detection and Systemic Awareness for the QUonG computing system, IEEE Proceedings (SRDS) International Symposium on Reliable Distributed Systems, Nara, Japan, October 6-9, 2014 - talk at Conference
  • Alessandro Lonardo, A FPGA-based Network Interface Card with GPUDirect enabling real-time GPU computing in HEP experiments, Perspectives of GPU Computing in Physics and Astrophysics, Roma, Italy, September 15-17, 2015 - talk at Conference
  • Francesco Simula, Distributed simulation of Polychronous and plastic Spiking Neural Networks: experiments with GPUs, in Perspectives of GPU Computing in Physics and Astrophysics, Rome, Italy, September 15-17, 2014 - talk at Conference
  • Alessandro Lonardo, A FPGA-based Network Interface Card with GPUDirect enabling real-time GPU computing in HEP experiments, GPUs in High Energy Physics, Pisa, Italy, September 10-12 , 2014 - talk at Conference
  • Piero Vicini, NaNet: a Low-Latency, Real-Time, Multi-Standard Network Interface Card with GPUDirect Features, at (RT2014) Real-Time Conference, Nara, Japan, May 26-30, 2014

2013

  • Roberto Ammendola - Virtual-to-Physical address translation for an FPGA-based interconnect with host and GPU remote DMA capabilities - 2013 International Conference on Field-Programmable Technology (ICFPT) 2013 - 9-11 dec - Kyoto, Japan
  • Alessandro Lonardo - Building a Low-latency, Real-time, GPU-based Stream Processing System - GTC 2013 - March 20, 2013 - San Jose (California)
  • Andrea Biagioni - The EURETILE hardware experimental platform - CASTNESS 2013 - 28 June 2013 - Barcelona, Spain
  • Laura Tosoratto - Fault and Critical Event Awareness: a no-single-point-of-failure approach for distributed systems - CASTNESS 2013 - 28 June 2013 - Barcelona, Spain
  • Andrea Biagioni - APEnet+ 34 Gbps Data Transmission System and Custom Transmission Logic - TWEPP 2013 - Sept 23-27, Perugia, Italy 2013
  • Francesco Simula - From GPU-accelerated computing to GPU-accelerated data acquisition for physics experiments; the QUonG cluster, the APEnet+ network card and the APE project evolution - X Seminar on Software for Nuclear, Subnuclear and Applied Physics 2013 - Alghero, Italy
  • Piero Vicini - Analysis of performance improvements for host and gpu interface of the APENet+ 3D Torus network - XV International Workshop on Advanced Computing and Analysis Techniques in Physics (ACAT)- Beijing, China - May 2013
  • Piero Vicini - GPU for Real Time processing in HEP trigger systems - XV International Workshop on Advanced Computing and Analysis Techniques in Physics (ACAT)- Beijing, China - May 2013
  • Davide Rossetti - GPU Techniques Applied to a Cluster Interconnect - Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW) 2013 - Boston, MA.
  • Alessandro Lonardo - Architectural improvements and 28 nm FPGA implementation of the APEnet+ 3D Torus network for hybrid HPC systems - International Conference on Computing in High Energy and Nuclear Physics (CHEP) 2013, 14-18 Oct 2013, Amsterdam, Nederlands.
  • Ottorino Frezza - Design and implementation of a modular, low latency, fault-aware, FPGA-based Network Interface - ReConFig 2013 - Dec 2013 - Cancun, MEX.

2012

  • R. Ammendola, apeNET+: a 3D toroidal network enabling petaFLOPS scale Lattice QCD simulations on commodity clusters, Lattice 2010, THE XXVIII INTERNATIONAL SYMPOSIUM ON LATTICE FIELD THEORY, Villasimius, Italy, June 2010, http://agenda.infn.it/contributionDisplay.py?contribId=335&sessionId=70&confId=2128
  • D. Rossetti, Leveraging NVIDIA GPUDirect on APEnet+ 3D Torus Cluster Interconnect - GTC 2012 - GPU Technology Conference - May 2012 - San Jose, CA, [[24]]
  • R. Ammendola, Comunicazioni Peer to Peer tra GPU remote con APENet+ - E4 Workshop 2012 - Sept 2012 - Bologna, Italy [[25]]
  • D. Rossetti, Multi GPU simulations: status and perspectives - New Frontiers in Lattice Gauge Theory, GGI Firenze, Italy - [[26]]
  • Davide Rossetti, Breadth First Search on APEnet+ - talk at IA^3 Workshop on Irregular Applications at SC12 conference, 10 Nov 2012. Presentation available here
  • Pier Stanislao Paolucci, Brain Inspired Many-Tile Experiment: second year overview of EURETILE, CASTNESS'12, 26 January 2012, Paris, France
  • P. Vicini, Peer-to-peer GPGPU-APENet+connectivity on HPC EURETILE platform, CASTNESS'12, 26 January 2012, Paris, France

2011

TIMA

2014

  • Frédéric Rousseau, "Lightweight task migration in multi-tiles architectures – communication consistency", MPSoC forum, Margaux – France, 7-11 July 2014.

2013

  • Ashraf Elantably, Frédéric Rousseau. Lightweight task migration in embedded multi-tiled architectures using task code replication, CASTNESS 2013, Barcelona, Spain.

2012

  • Frédéric Rousseau, Requirements in Communication Synthesis for EURETILE: The use of Communication Path Formalization, CASTNESS 2012, January 26th, 2012, Paris, France
  • Frédéric Rousseau, presentation of the EURETILE project in front of the Board of directors of the University Joseph Fourier, March 2011, Grenoble, France (in French)
  • Frédéric Rousseau, Communication Synthesis in Low Level Software for Hierarchical Heterogeneous Systems, CASTNESS 2011, January 17-18, 2011, Rome, Italy

Target

2011

  • G. Goossens, “Why Compilation Tools are the Catalyst for Multicore SoC Design”, Electronic Design and Solutions Fair, Yokohama (Japan), January 27-28, 2011.
  • G. Goossens, “Why Compilation Tools are a Catalyst for Multicore SoC Design”, Third Friday Workshop on Designing for Embedded Parallel Computing Platforms: Architectures, Design Tools, and Applications, Design Automation and Test in Europe (DATE-2011), Grenoble (France), March 18, 2011.
  • G. Goossens, P. Verbist, “Enabling the Design and Programming of Application-Specific Processors”, Sophia-Antipolis Micro-Electronics Conference (SAME-2011), Sophia-Antipolis (France), October 12-13, 2011.
  • G. Goossens, “Building Multicore SoCs with Application-Specific Processors”, Electronic Design and Solutions Fair, Yokohama (Japan), November 16-18, 2011.
  • P. Verbist, “Building software-programmable accelerators for ARM-based subsystems”, ARM Technical Symposium, Taipei and Hsinchu (Taiwan), November 17-18, 2011.
  • G. Goossens, “Building Multicore SoCs with Application-Specific Processors”, Intl. Conf. on IP-Based SoC Design (IP-SoC-2011), Grenoble (France), December 7-8, 2011.
  • G. Goossens, “Design Tools for Building Software-Programmable Accelerators in Multicore SoCs”, Workshop on Tools for Embedded System Design, Sint-Michielsgestel (Netherlands), December 13, 2011.

2010

  • G. Goossens, "How ASIP Technology can Make your RTL Blocks More Flexible", Electronic Design and Solutions Fair, Yokohama (Japan), January 28-29, 2010.
  • S. Cox, G. Goossens, "Hardware Accelerator Performance in a Programmable Context: Methodology and Case Study", Embedded Systems Conference, San Jose (CA, USA), April 26-29, 2010.
  • G. Goossens, "Design of Programmable Accelerators for Multicore SoCs", First Artemis Technology Conference, Budapest (Hungary), June 29-30, 2010.
  • W. Geurts, G. Goossens, "Ideas for the Design of an ASIP for LQCD", CASTNESS 2011, Rome (Italy), January 17-18, 2011, http://euretile.roma1.infn.it/mediawiki/img_auth.php/3/3c/EURETILE-5-WernerGeurts.ppt
  • G. Goossens, E. Brockmeyer, W. Geurts, “Application-Specific Instruction-set Processors (ASIPs) and related design tools for tiled systems”, CASTNESS 2012, Paris (France), January 26, 2012.

Books

  • ETHZ
    • Book chapter: I. Bacivarov, W. Haid, K. Huang, L. Thiele. Methods and Tools for Mapping Process Networks onto Multi-Processor Systems-On-Chip. Handbook of Signal Processing Systems, Springer, pages 1007-1040, October, 2010.
  • RWTH
    • Book chapter: J. H. Weinstock, C. Schumacher, R. Leupers and G. Ascheid: "SCandal: SystemC Analysis for Nondeterminism Anomalies", in Models, Methods, and Tools for Complex Chip Design (Haase, J., ed.) vol. 265 of Lecture Notes in Electrical Engineering. Springer, 2013.
    • Book: T. Kempf, G. Ascheid, R. Leupers: Multiprocessor Systems on Chip: Design Space Exploration, Springer, Feb 2011, ISBN 978-1441981523
    • Book: R. Leupers and O. Temam (Eds.), Processor and System-On-Chip Simulation, Springer, September 2010, ISBN 978-1441961747
  • TIMA
    • Katalin Popovici, Frederic Rousseau, Ahmed A. Jerraya, Marilyn Wolf: Embedded Software Design and Programming of Multiprocessor System-on-Chip, Simulink and SystemC Case Studies, Springer, April 2010, ISBN 978-1-4419-5566-1
    • Book chapter: Xavier Guerin, Frederic Petrot, Operating System Support for Applications targeting Heterogeneous Multi-Core System)on-Chip in the book Multi-Core Embedded Systems, CRC Press, Chapter 9, 24 pages, April 2010.

CASTNESS'11 Workshop

Private Zone
navigation (public zone)
Project Partners