EUropean REference TILed architecture Experiment (2010-2013)
NEWS
- Several EURETILE presentations at CASTNESS'12 workshop, right after HIPEAC'12 (Jan 26th, 2012): http://teraflux.eu/castness
download here all the presentations of the previous year edition: CASTNESS'11
CASTNESS'11 is a dissemination event jointly organized by the 4 Fet Tera Device Computing projects
EURETILE Abstract
Grant Agreement no. 247846 Call: FP7-ICT-2009-4 Objective FET-ICT-2009.8.1 Concurrent Tera-device Computing
EURETILE investigates and implements brain-inspired foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution target is a fault-tolerant many-tile HW platform, equipped with a many-tile simulator. A set of SW process - HW tile mapping candidates are generated by the holistic SW tool-chain using a combination of analytic and bio-inspired methods. The Hardware dependent Software is then generated, providing OS services with maximum efficiency/minimal overhead. The many-tile simulator collects profiling data, closing the loop of the SW tool chain. Fine-grain parallelism inside processes is exploited by optimized intra-tile compilation techniques, but the project focus is above the level of the elementary tile. The elementary HW tile is a multi-processor, which includes a fault tolerant Distributed Network Processor (for inter-tile communication), a floating-point numerical engine (for computations) and a RISC processor (for control, user interface and sequential computations). Furthermore, EURETILE investigates and implements the innovations for equipping the elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex. EURETILE leverages on the working SW and HW prototypes of the innovative multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPES Integrated Project (2006-2009). This background knowledge includes working tile silicon and board, a multi-tile simulator (running up to eight tiles), and a complete SW tool-chain including a parallel programming and an automatic mapping/optimization environment (Distributed Operation Layer), a specialized OS (DNA-OS automatically generated for both RISC and VLIW floating-point numerical processor) integrated with Linux RT, and an optimizing compiler co-designed with the floating-point engine. INFN (Istituto Nazionale di Fisica Nucleare) is the coordinator of the project. The APE Parallel Computing Lab of INFN Roma is in charge of the EURETILE HW Design and Scientific Application Benchmarks. The Computer Engineering and Networks Laboratory (TIK) of ETH Zurich (Swiss Federal Institute of Technology) designs the high-level explicit parallel programming and automatic mapping tool (DOL/DAL). The Software for Systems on Silicon (SSS) of the ISS institute of RWTH Aachen, investigates and provide the parallel simulation technology. The TIMA Laboratory of the University Joseph Fourier in Grenoble explores and deploys the HdS (Hardware dependent Software) including the distributed OS architecture. TARGET Compiler Technologies, the Belgian leading provider of retargetable software tools and compilers for the design, programming, and verification of application-specific processors (ASIPs), is in charge of the HW/SW Co-design tools for custom components of the EURETILE architecture.
Participating Institutions
Collaboration partners: INFN, ETH Zurich, RWTH Aachen, TARGET, TIMA
People
Links:
- The EURETILE people page.
ENTER THE PRIVATE SITE HERE
Project Coordinator: Pier Stanislao Paolucci - INFN (Istituto Nazionale di Fisica Nucleare)
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